(1) Field of the Invention
The present invention relates to a MOS type solid-state imaging device intended for a digital camera.
(2) Description of the Related Art
A Metal-Oxide-Semiconductor (MOS) type solid-state imaging device is an image sensor that amplifies and reads out each signal of photon electric charge accumulated in a photodiode within each pixel, using an amplifier circuit that includes an insulated gate field effect transistor formed in each pixel (to be referred to as “MOS transistor” hereinafter). A Complementary MOS (CMOS) image sensor manufactured in the CMOS process, in particular, draws attention as an image input device for a portable device such as a small camera for a Personal Computer (PC). This is the case because it is a device that needs low voltage as well as little electricity to work, and offers an advantage in that it can be constructed, together with its periphery circuit, in chip form.
FIG. 1 is a cross-sectional view showing an example of the structure of an N-channel MOS transistor composing an imaging region of the conventional MOS type solid-state imaging device and a trench isolation unit. As shown in FIG. 1, a P type well region is formed on a silicon substrate 8. In the P type well region, the N-channel MOS transistor is formed and a source region of the N-channel MOS transistor forms a part of a photodiode 10. In the photodiode 10, photons are converted into electric charge (i.e., electric charge is generated by exposure to light). In general, an oxide film formed by LOCal Oxidation of Silicon (LOCOS) is used for a trench isolation unit which isolates the neighboring elements (e.g., MOS transistors). Along with the miniaturization of the solid-state imaging device, an oxide film formed by Shallow Trench Isolation (STI) can also be used for the device isolation region, as can be seen in the trench isolation unit 9 shown in FIG. 1.
FIG. 2 is a diagram showing an example of the structure of the conventional MOS type solid-state imaging device. The MOS type solid-state imaging device is comprised of: an imaging region 27 where plural pixels 26 are two-dimensionally arranged on the silicon substrate 8; a vertical shift register 28 and a horizontal shift register 29 for selecting pixels; and a timing generation circuit 30 for providing pulses necessary for the shift registers. Each pixel 26 in the imaging region 27 is composed of a photoelectric conversion unit 31 and four MOS transistors including a transfer transistor 32, a reset transistor 23, an amplifier transistor 24, and a select transistor 25.
In the imaging region 27, a film stress due to a nitride film or the like, an ion implantation, or an etching process causes defects in the MOS type solid-state imaging device formed by using the LOCOS or the STI for the device isolation region. The defects cause dark currents or white flaws. Moreover, the use of the LOCOS causes difficulty in the miniaturization of the imaging region 27 because a bird's beak width gets longer. The use of the STI causes a problem that stress is generated due to an embedded oxide film.
A method to overcome the problems is disclosed in Japanese Laid-Open Publication No. 2000-196057 (conventional example 1). The method described in the conventional example 1 will be explained with reference to FIGS. 3A–3F. FIGS. 3A–3F respectively show cross-sectional views showing how the device isolation region according to the MOS type solid-state imaging device in the conventional example 1 is built during the manufacturing process.
As shown in FIG. 3A, a SiO2 film is deposited on a semiconductor substrate 61 as a gate dielectric film 52 by means of thermal oxidation so that the thickness of the film becomes 0.1 μm. Then, a channel stopper 53, a photoelectric conversion unit 54 and a drain 55 are formed by performing ion implantation via the gate dielectric film (thermal oxide film) 52. As shown in FIG. 3B, a CVD oxide film 56 is then deposited on the gate dielectric film so that the thickness becomes approximately 0.3 μm. After the deposit of the CVD oxide film (resist) 56, etching is performed on the CVD oxide film 56 and the gate oxide film 52 based on a Reactive Ion Etching (RIE) method using a mask so that a gate channel 57 is opened.
As shown in FIG. 3D, a gate oxide film is then formed in the channel region by performing oxidation again after having deposited a gate electrode 58 made of polysilicon. After that, as shown in FIG. 3E, a polysilicon wiring pattern is formed by performing, using a resist mask, the RIE on the gate electrode 58 with a pattern that is at least larger than the gate channel 57. As shown in FIG. 3F, an interlayer dielectric 59 made of SiO2 and others is deposited and then is partly opened using the RIE method so that the dielectric film 59 is conducted with the drain 55 and a signal line 60 is embedded.
In general, the MOS type solid-state imaging device has an amplifier circuit in each pixel, and is characterized in that a high sensitivity can be realized by amplifying small electric signals. Therefore, in the case where the amount of the leak current leaking into the photodiode is large, the leak current is also amplified and large noises are caused. Due to the noises, the deterioration of the image is a crucial issue. Here, the leak current means all the currents that leak into the photodiode apart from the current generated by converting photons into electric charge in the photodiode.
The study of the miniaturization and the increase in density of the semiconductor device, along with the demand for high performance information processing techniques and miniaturization of portable devices, has presently been underway as energetically as ever. The development of the CMOS type solid-state imaging device in compliance with the 0.18 μm (or below) design rules is currently underway. Further miniaturization of the pixel area and the periphery circuit is one of the targets for the present solid-state imaging device. The high integration and high density of the solid-state imaging device due to such miniaturization is an effective means to achieve high performance, such as high speed or multi-function, in the solid-state imaging device, and is indispensable for manufacturing future solid-state imaging devices.
However, the degradation of the sensitivity due to the decrease in the surface of the imaging region is a problem specific to the miniaturization as described above. For example, the sensitivity in the photodiode region indicates the smallest quantity of photon electric charge in which an amount of photoelectric converted charge surpasses an amount of noise charge caused by the leak current. The decrease in the amount of noise electric charge is indispensable for improving the sensitivity.
As described above, the miniaturized MOS transistor has been developed utilizing miniaturization technology for semiconductor LSI, and the reality is that no attention has been paid to the leak current. For instance, the STI, which has already been explained as being used for a device isolation structure suitable for the miniaturization of the solid-state imaging device, is widely used for the semiconductor devices. The STI, however, due to its structure in which a trench is formed in a silicon substrate by performing dry etching and the trench is filled with an oxide film, causes high stress within the silicon substrate because of the difference in thermal expansion coefficient between the filled oxide film and the silicon substrate. The stress concentrates on the corners of the bottom part of the trench due to their steep angles. The existence of the stress that is resistant to crystals increases the density of crystal defect for stabilizing crystal energy. The electrons generated due to the crystal defect are one of the causes of the leak current.
The interface state that is not involved in bonding is formed as the interface between the silicon substrate and the embedded oxide film where non-bonding electrons exist. With the STI, the crystal structure on or in the vicinity of the interface between the silicon substrate and the embedded oxide film is extremely disordered, since the trench isolation unit is formed by means of dry etching.
This is why many non-bonding electrons that are not involved in bonding are found on or in the vicinity of the interface (the non-bonding electrons on and in the vicinity of the interface is termed “interface state leak”). A large leak current is caused by this interface state leak.
As described above, the solid-state imaging device having the MOS transistor miniaturized by the semiconductor LSI technique faces a problem that the leak current caused by the crystal defect induced by the stress and the leak current generated from the interface state with the STI which includes the silicon surface cause much larger noises. According to the MOS type solid-state imaging device and the manufacturing method, as described in the background art above, the device isolation region is formed by means of channel stop implanting. Further, it is necessary to widen the width of the device isolation region in order to retain enough withstanding pressure in the device isolation region.